Abstract
We propose a voltage reference based on the weighted difference between the gate-source voltages of an nMOS and a pMOS operating in their saturation regions. No diodes or parasitic bipolar transistors are used. The circuit is simulated and fabricated with SMIC 0.18 μm mixed-signal technology, and our measurements demonstrate that its temperature coefficient is 44 ppm/°C and its PSRR is -46 dB. It works well when Vdd is above 650 mV. The active area of the circuit is about 0.05 mm2.
Original language | English |
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Pages (from-to) | 774-777 |
Number of pages | 4 |
Journal | Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors |
Volume | 27 |
Issue number | 5 |
State | Published - May 2006 |
Externally published | Yes |
Keywords
- Power supply rejection ratio
- Temperature coefficient
- Voltage reference