Statistical modeling of grain-enhanced polysilicon thin-film transistor in consideration of grain boundary distribution

A probabilistic model to predict the statistical distribution of grain boundaries in the thin-film transistor (TFT) with an arbitrary transistor-to-grain size ratio is proposed in this paper. Performance of the TFTs, such as carrier mobility, can be estimated and the corresponding performance variation of the fabricated devices becomes predictable when the statistical distribution of grain boundaries is known. The proposed model is still applicable even when the transistor size becomes comparable to the grain size. Reliability and accuracy of the modeling results have been extensively verified by experimental data. It is believed that the model can provide design and optimization guidelines of device variation for grain-enhanced polysilicon TFT technology.