Impact of integrated superlattice μTEC structures on hot spot remediation

Driven by shrinking feature sizes, microprocessor "hot-spots" - with their associated high heat flux and sharp temperature gradients - have emerged as the primary "driver" for on-chip thermal management of today's advanced IC technology. Proposed uses of solid state thermoelectric microcoolers for hot spot remediation have included the formation of a superlattice layer on the back of the microprocessor chip, but there have been few studies on the cooling performance of such devices. The present study provides the results of three-dimensional, electro-thermal, finite-element modeling of a superlattice microcooler, focusing on the achieved hot spot temperature and superlattice surface temperature reductions, respectively. Simulated temperature distributions and heat flow patterns in the silicon, associated with variations in microcooler geometry, chip thickness, hot spot size, hot spot heat flux, and superlattice thickness are provided. Comparison is made to hot spot cooling achieved by the Peltier effect in the silicon microprocessor chip itself. The numerical results suggest that, for a variety of operating conditions and geometries, while increasing the superlattice thickness serves to decrease the exposed superlattice surface temperature, it is ineffective in reducing the hot spot temperature below that due to the silicon Peltier effect.