TY - GEN
T1 - Enhanced thermoelectric cooler for on-chip hot spot cooling
AU - Wang, Peng
AU - Bar-Cohen, Avram
AU - Yang, Bao
PY - 2007
Y1 - 2007
N2 - Due to shrinking feature size and increasing transistor density, combined with the performance demanded from nextgeneration microprocessors, on-chip hot spots, with their associated high heat fluxes and sharp temperature gradients, have emerged as me primary driver for thermal management of today's IC technology. This paper describes the novel use of thermoelectric coolers for on-chip hot spot cooling through the use of a copper mini-contact pad, which connects the thermoelectric cooler and the silicon chip thus concentrating the thermoelectric cooling power. A package-level numerical simulation is developed to predict the local on-chip hot spot cooling performance which can be achieved with such mini-contacts. Attention is focused on the hot spot temperature reduction associated with variations in mini-contact size and the thermoelectric element thickness, as well as the parasitic effect of the thermal contact resistance introduced by the mini-contact enhanced TEC. This numerical model and simulation results are validated by comparison to spot cooling experiments with a uniformly heated chip serving as the test vehicle. The experimental results demonstrate that a copper mini-contact pad can improve spot cooling performance by 80-115% on a 500pm thick silicon chip under optimum operating conditions and that larger power dissipation on the chip leads to better spot cooling performance.
AB - Due to shrinking feature size and increasing transistor density, combined with the performance demanded from nextgeneration microprocessors, on-chip hot spots, with their associated high heat fluxes and sharp temperature gradients, have emerged as me primary driver for thermal management of today's IC technology. This paper describes the novel use of thermoelectric coolers for on-chip hot spot cooling through the use of a copper mini-contact pad, which connects the thermoelectric cooler and the silicon chip thus concentrating the thermoelectric cooling power. A package-level numerical simulation is developed to predict the local on-chip hot spot cooling performance which can be achieved with such mini-contacts. Attention is focused on the hot spot temperature reduction associated with variations in mini-contact size and the thermoelectric element thickness, as well as the parasitic effect of the thermal contact resistance introduced by the mini-contact enhanced TEC. This numerical model and simulation results are validated by comparison to spot cooling experiments with a uniformly heated chip serving as the test vehicle. The experimental results demonstrate that a copper mini-contact pad can improve spot cooling performance by 80-115% on a 500pm thick silicon chip under optimum operating conditions and that larger power dissipation on the chip leads to better spot cooling performance.
KW - BiTe
KW - Mini-contact
KW - Onchip hot spot
KW - Thermal contact resistance
KW - Thermal management
KW - Thermoelectric cooer
UR - https://www.scopus.com/pages/publications/40449130937
U2 - 10.1115/IPACK2007-33798
DO - 10.1115/IPACK2007-33798
M3 - Conference contribution
AN - SCOPUS:40449130937
SN - 0791842770
SN - 9780791842775
T3 - 2007 Proceedings of the ASME InterPack Conference, IPACK 2007
SP - 249
EP - 258
BT - 2007 Proceedings of the ASME InterPack Conference, IPACK 2007
T2 - ASME Electronic and Photonics Packaging Division
Y2 - 8 July 2007 through 12 July 2007
ER -