Design and application of instruction set simulator on multi-core verification

Xiang Dong Hu, Yong Guo, Ying Zhu, Xin Guo, Peng Wang

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


Instruction Set Simulator (ISS) is a highly abstracted and executable model of micro architecture. It is widely used in the fields of verification and debugging during the development of microprocessors. However, with the emergence of Chip Multi-Processors, the single-core ISS cannot meet the needs of microprocessor development. In this paper, we introduce our multi-core chip architecture first, after that a general methodology to expand a single-core ISS to a multi-core ISS (MCISS) is proposed. On this basis, a real-time comparison environment is created for multi-core verification, and the problems of multi-core communication and synchronization are addressed gracefully. With the "save and restore" mechanism, the verification procedure and the debugging are speeding up greatly.

Original languageEnglish
Pages (from-to)267-273
Number of pages7
JournalJournal of Computer Science and Technology
Issue number2
StatePublished - Mar 2010
Externally publishedYes


  • Chip multi-processors (CMP)
  • Instruction set simulator (ISS)
  • Parallel stimulus
  • Processor design
  • Simulation


Dive into the research topics of 'Design and application of instruction set simulator on multi-core verification'. Together they form a unique fingerprint.

Cite this